1. Field of the Invention
The present invention relates generally to semiconductor circuits and packaged integrated circuits, such as memory chips, data registers and the like. More particularly, the present invention relates to circuitry used for enabling test mode operations in such parts.
2. Description of the Related Art
Testing and potentially modifying internal parameters of memory chips for the purpose of circuit optimization is critically important. This is particularly important because memory chips are becoming more complex and the time to market is a very critical factor in the success of any chip. In some chips, this is done by making modifications to masks such as metal or contact. The masks are processed toward the end of the fabrication process and making changes to the circuitry using these masks does not add too much of a time penalty. Although this is a valid solution, it still fails to allow for maximum flexibility or minimize turnaround times.
With memories such as non-volatile memories, more flexibility is added through the use of such memory elements in modifying circuit parameters. By programming a specific pattern in these memory elements, one can change the configuration of the circuitry and even the configuration of the entire chip. Such modifications are usually done in the factory before the part is shipped to a customer or end user. The accidental modification of any of these settings by an end user can have devastating effects on the operation of the chip and must be avoided. Therefore, the modification of these settings are done through non-user modes of operation referred to herein as test modes.
Test modes are typically used for stressing or changing the internal settings of the parts. The accidental or even intentional use of such modes by an end user could damage the part. Therefore, test modes should have safeguards which minimize the chances of accidental entry of the test modes by end users.
U.S. patent application Ser. No. 08/386,704, filed Feb. 10, 1995, for "APPARATUS FOR ENTERING AND EXECUTING TEST MODE OPERATIONS FOR MEMORY", discloses a scheme to enter and execute different test modes that minimizes the chances of accidental user entry of the test modes. The contents of this application are hereby fully incorporated into the present application by reference.
The test mode enable scheme disclosed in application Ser. No. 08/386,704 provides safeguards to assure that test modes can only be activated when specific conditions are present that are not usually performed by an end user. As a hardware safeguard, some of the voltages applied to the chip must be raised to values higher than the regular voltages applied to the pins of that chip during normal operations. If this-were the only safeguard, however, then a noisy set-up may potentially trigger a test mode. Thus, the scheme disclosed in application Ser. No. 08/386,704 utilizes a software safeguard in combination with the hardware safeguard.
Although the test mode enable scheme disclosed in application Ser. No. 08/386,704 provides sufficient protection against accidental user entry of test modes, not all test setups have the ability to provide the high voltages required to place the part in a test mode. One solution is to not use the high voltage safeguard and rely solely on the software safeguard. The disadvantage of this solution is that one does not want to rely solely on software to enter and execute test modes since the end user might enter the test modes accidentally.
Thus, there is a need for a test mode enable scheme which does not require that high voltages be applied to the part in order to enter a test mode, but which still provides maximum hardware and software protection in order to minimize the chances of accidental entry of test modes by an end user. Such a scheme should provide a hardware protection so that test modes cannot be accessed by software alone.